1. Field of the Invention
The present invention relates to a multilayer capacitor array.
2. Related Background Art
As electronic devices have been reducing their size and thickness, capacitors mounted on them have been desired to be integrated. Therefore, a capacitor array including a plurality of capacitors within one chip has recently been under study. For example, one comprising a multilayer body in which inner electrode layers each provided with a plurality of inner electrodes arranged in parallel and dielectric layers are alternately laminated, and a plurality of terminal conductors formed on the multilayer body has been known (see, for example, Japanese Patent Application laid-Open No. HEI 11-26291).
On the other hand, power supplies for central processing units (CPUs) mounted in digital electronic devices have been lowering their voltage while increasing their load current. This has made it very difficult for fluctuations in power voltage to be held below a tolerable level, whereby a multilayer capacitor known as decoupling capacitor has been connected to the power supplies. When the load current fluctuates transiently, the multilayer capacitor supplies a current to the CPU, thereby suppressing the fluctuation in power voltage.
Recently, as the CPUs have further been increasing their frequency, their load current has been becoming faster and greater. Therefore, the multilayer capacitors employed in decoupling capacitors have been demanded to increase their capacity and equivalent series resistance (ESR).